Today's SoCs are very large and complex with large number of IP blocks, memory blocks, and logic connected using one or more interconnect bus fabric. Many of the IP blocks are third party IPs with RTLs licensed from vendors. These base IPs are then customized or hardened to suit the use in the SoC by instantiation of additional memory blocks, adding pipelining to speed up the operation, customizing the bus width and the number of cores and by specifying shape of intellectual property (IP) block and placement of inputs and outputs (I/Os) pins. These IPs typically end up having complexities similar to the SoC itself but on a smaller scale, in that these can have 10s of millions of placeable instances, hundreds of memory blocks or macros, multiple clock trees with differing clock frequencies and multiple power domains. The teams that work on hardening and design closure of the IPs and SoCs typically are different from the RTL designers and have limited access and knowledge of the internal structure of the IP. This makes the process of design closure very complex and time consuming.
FIG. 1 is a block diagram of a SoC 100. It has a circuit block 101 and inputs and outputs I/Os 102. A typical circuit block 101 of the SoC design 200 is shown in FIG. 2 and an exemplary and non-limiting block diagram of a SoC layout 300 is shown in FIG. 3. The circuit block 101 comprise memory blocks 120, intellectual property (IP) blocks 130, specialized distributed logic blocks 140 such as I/O logic 141 and glue logic 142, and standard cell logic 150 all interconnected by an interconnect fabric 110. The IP blocks 130 in the SoC 100 themselves are highly complex SoC level blocks with IP blocks 132, memory blocks 133, and standard cell logic 134, all interconnected using an interconnect fabric 131. The typical SoCs of today require RTL synthesis that generates a gate level net-list of the design, floor-planning, detailed placement of the IPs memory and logic and routing to interconnect the completed design. The current circuit design flows typically do not allow design closure and validation before the detailed place and route is complete even though the critical paths are typically the global routes within the SoC 100. The timing closure and validation, that is meeting area, timing, congestion and power constraints can only be checked after place and route and it is by iterative sequence of these operations that the final design closure can be achieved. Though there have been programs that enable wire modeling providing delay estimates of interconnects, these have not been accurate enough to provide estimates that are realistic below 45 nm technology node as the wiring parasitic dominate the delays. This is also due to the need to have hard IPs 130 inside the SOC 100 which introduces discontinuity in the routing schemes, unlike the standard cells which follow specific routing rules and provide continuity. The hard macros hence limit routability over the IPs 130 placed within the circuit blocks 101 of the SOC 100 and make estimation of routing delays difficult at any time prior to completion of place and route. This makes it impossible to have design closure and validation without completing the final physical planning and place and route of the SoC 100.
It will make design closure of large SoCs faster and cheaper if a method and system can be found that enables physical floor planning and routing, especially global routing of the logic and interconnectivity of the hard IPs during the early design period without waiting till the detailed design and physical layout of the chip is completed. Such a system and method that provides a means to start the physical planning early in the design cycle and also provide a methodology towards achieving early design closure, at higher levels of abstraction, will be of great use in completing a SoC design early, with lower cost of resources.